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NCP2824 Non-Clip and Power Limit Mono Class D Amplifier with AGC
Description
The NCP2824 is a Filterless Class D amplifier capable of delivering up to 2.4 W to a 4 W load with a 5 V supply voltage. With the same battery voltage, it can deliver 1.2 W to an 8 W load with less than 1% THD+N. The non-clipping function automatically adjusts the output voltage in order to control the distortion when an excessive input is applied to the amplifier. This adjustment is done thanks to an Automatic Gain Control circuitry (AGC) built into the chip. A simple Single wire interface allows to the non Clipping function to be enabled and disabled. It also allows the maximum distortion level in the output to be configured. A programmable power limit function is also embedded in order to protect speakers from damage caused by an excessive sound level.
Features
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1 9 PIN FLIP-CHIP FC SUFFIX CASE 499AL
PIN CONFIGURATION
A1 B1 C1 A2 B2 C2 (Top View) A1 = INP A2 = VDD A3 = OUTP B1 = AGND B2 = NC B3 = PGND C1 = INM C2 = CNTL C3 = OUTM A3 B3 C3
* * * * * * * * * * * * * * *
Non Clipping Function with Automatic Gain Control Circuitry Programmable Power Limit Function Single Wire Interface. No Need for Additional Components Max THD+N Configurable by Swire Interface Only One Capacitor Required Fully Differential Architecture: Better RF Immunity No Need for Input Capacitors in Fully Differential Configuration High Efficiency: up to 90% Low Quiescent Current: 2.2 mA Typ Large Output Power Capability High PSRR: up to -80 dB Fully Differential Capability: RF Immunity Thermal and Auto Recovery Short-Circuit Protection CMRR (-80 dB) Eliminates Two Input Coupling Capacitors Pb-Free and Halide-Free Device
MARKING DIAGRAM
A1
A3
MRAG FYWW
C1
Typical Applications
MRA F Y WW G or G
= Specific Device Code = Assembly Location = Year = Work Week = Pb-Free Package
Audio Amplifier for: * Cellular Phones * Digital Cameras * Personal Digital Assistant and Portable Media Player * GPS
Demo Board Available:
ORDERING INFORMATION
Device NCP2824FCT2G Package WCSP-9 (Pb-Free) Shipping 3000/Tape & Reel
* The NCP2824GEVB/D evaluation board configures the device in
typical application.
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2010
September, 2010 - Rev. 0
1
Publication Order Number: NCP2824/D
NCP2824
C1 4.7 mF/6.3 V
VDD
Auto Gain control
INN INP PreAmplificator PWM Modulator H BRIDGE
OUTN OUTP
CNTL
Single Wire Interface
Auto Gain control
GND
Figure 1. Simplified Block Diagram
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Table 1. PIN FUNCTION DESCRIPTION
Pin A1 C1 A2 B2 A3 C3 C2 B3 Pin Name INP INN PVDD NC OUTP OUTN CNTL PGND Type Input Input POWER - Output Output Input POWER Positive Input Negative Input Power Supply: This pin is the power supply of the device. A 4.7 mF ceramic capacitor or larger must bypass this input to the ground. This capacitor should be placed as close a possible to this input. Non-connected: reserved for production. Must be kept floating in the final application Positive output: Special care must be observed at layout level. See the Layout consideration section Negative output: Special care must be observed at layout level. See the Layout consideration section Control: This pin is dedicated to the control of the chip via the Single wire protocol Power Ground: This pin is the power ground and carries the high switching current. A high quality ground must be provided to avoid any noise spikes/uncontrolled operation. Care must be observed to avoid high-density current flow in a limited PCB copper track. Analog Ground: This pin is the analog ground of the device and must be connected to GND plane. Description
B1
AGND
POWER
Table 2. MAXIMUM RATINGS
Rating AVDD, PVDD Pins: Power Supply Voltage (Note 2) INP/N Pins: Input (Note 2) Digital Input/Output: EN Pin: Input Voltage Input Current Human Body Model (HBM) ESD Rating are (Note 3) Machine Model (MM) ESD Rating are (Note 3) WCSP 1.5 x 1.5 mm package (Notes 6 and 7) Thermal Resistance Junction to Case Operating Ambient Temperature Range Operating Junction Temperature Range Maximum Junction Temperature (Note 6) Storage Temperature Range Moisture Sensitivity (Note 5) Symbol VDD VINP/N VDG IDG ESD HBM ESD MM RqJC TA TJ TJMAX TSTG MSL Value -0.3 to +6.0 -0.3 to +VDD -0.3 to VDD + 0.3 1 2000 200 90 -40 to +85 -40 to +125 +150 -65 to +150 Level 1 C C C C Unit V V V mA V V C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = 25C. 2. According to JEDEC standard JESD22-A108B. 3. This device series contains ESD protection and passes the following tests: Human Body Model (HBM) 2.0 kV per JEDEC standard: JESD22-A114 for all pins. Machine Model (MM) 200 V per JEDEC standard: JESD22-A115 for all pins. 4. Latch up Current Maximum Rating: 100 mA per JEDEC standard: JESD78 class II. 5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J-STD-020A. 6. The thermal shutdown set to 150C (typical) avoids irreversible damage on the device due to power dissipation. 7. The RqCA is dependent on the PCB heat dissipation. The maximum power dissipation (PD) is dependent on the min input voltage, the max output current and external components selected.
R qCA +
125 * T A * R qJC PD
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Table 3. ELECTRICAL CHARACTERISTICS (Min & Max Limits apply for TA between -40C to +85C and for VDD between 2.5 V to 5.5 V (Unless otherwise noted). Typical values are referenced to TA = +25C and VDD = 3.6 V. (see Note 8))
Symbol Parameter Conditions Min Typ Max Unit GENERAL PERFORMANCES VDD FOSC Idd Isd TON TOFF Zsd RDS(ON) h Operational Power Supply Oscillator Frequency Supply current Shutdown current Turn ON Time Turn Off Time Class D Output impedance in shutdown mode Static drain-source on-state resistance of power Mosfets Efficiency VDD = 3.6 V, Po = 800 mW, RL = 8 W, F = 1 kHz VDD = 3.6 V, Po = 1.3 W, RL = 4 W, F = 1 kHz FLP TSD TSDH -3 dB Cut off Frequency of the Built in Low Pass Filter Thermal Shut Down Protection Thermal Shut Down Hysteresis VDD = 3.6 V, No Load VDD = 5.5 V, No Load, TA = 85C VDD = 3.6 V, VCNTL = 0 V VDD = 5.5 V, VCNTL = 0 V, TA = 85C Single Wire Activation Single Wire Deactivation VENL = 0 V 2.5 250 300 2.2 4.2 0.01 1 7.4 5 20 250 86 79 kHz 30 150 20 C C ms ms kW mW % mA 5.5 350 V kHz mA
AGC SECTION Av Av Aa Avn TA TR TH VIH VIL VIHYS RPLD TR TF TSWH TSWL Voltage gain Voltage gain Max AGC attenuation AGC Gain step resolution Attack time Release Time Hold Time Single Wire 4 Single Wire 5 12 18 -15 0.5 0.033 0.013 0.013 dB dB dB dB ms/Step s/Step s/Step
S-WIRE INTERFACE (see Note 9) Rising Voltage Input Logic High Falling Voltage Input Logics Low Input Voltage Hysteresis Pull Down Resistor Swire Rising time Swire Falling time Swire High Swire Low 5 5 10 10 1.2 0 - - 100 20 200 200 45 75 5.5 0.4 V V mV kW ns ns ms ms
8. Performances guaranteed over the indicated operating temperature range by design and/or characterization, production tested at TJ = TA = 25C. 9. Single Wire performances is guaranteed by design and characterized 10. Audio performances are given for Vdd = 3.6 V, TA = 25C and characterized
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Table 3. ELECTRICAL CHARACTERISTICS (Min & Max Limits apply for TA between -40C to +85C and for VDD between 2.5 V to 5.5 V (Unless otherwise noted). Typical values are referenced to TA = +25C and VDD = 3.6 V. (see Note 8))
Symbol Parameter Conditions Min Typ Max Unit S-WIRE INTERFACE (see Note 9) FSWF TEHDT TSDD TWAKE-UP TVALID voo PSRRDC PSRRAC SNR CMRR Vn Input S-wire Frequency Enable High Delay Time Time to Shunt Down Delay Time to Wake up from shutdown Time to Valid Data 300 0 300 100 400 400 500 400 kHz ms ms ms ms
AUDIO PERFORMANCES (see Note 10) Output offset Power supply rejection ratio Power supply rejection ratio Av = 12 dB From VDD = 2.5 V to 5.5 V F = 217 Hz, Input ac grounded, Av = 12 dB F = 1 kHz, Input ac grounded Av = 12 dB Signal to noise ratio Common mode rejection ratio Output Voltage noise Vp = 5 V, Pout = 600 mW (A. Weighted) Av = 12 dB Input shorted together VIC = 1 Vpp, f = 217 Hz Input ac grounded, Av = 12 dB 20 Hz < f < 20 kHz A. Weighted RL = 8 W F = 1 kHz THD+N<1% VDD = 5 V VDD = 3.6 V VDD = 2.5 V THD+N<10% VDD = 5 V VDD = 3.6 V VDD = 2.5 V RL = 4 W F = 1 kHz THD+N<1% VDD = 5 V VDD = 3.6 V VDD = 2.5 V THD+N<10% VDD = 5 V VDD = 3.6 V VDD = 2.5 V THD+N Total harmonic distortion plus noise VDD = 3.6 V, Po = 0.5 W VDD = 5 V, Po = 1 W 0.3 -80 -70 -70 96 -80 34 dB dB mV mV dB dB
Po
Output Power
1.2 0.6 0.22 1.5 0.8 0.4 2 1 0.4 2.4 1.3 0.6 0.06 0.09
W
%
8. Performances guaranteed over the indicated operating temperature range by design and/or characterization, production tested at TJ = TA = 25C. 9. Single Wire performances is guaranteed by design and characterized 10. Audio performances are given for Vdd = 3.6 V, TA = 25C and characterized
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NCP2824
TSWH TSWL TF TR
90% VIH VIL
10%
Figure 2. S-Wire Logic Diagram
Initial Stage / Tvalid Ton Amplifier Mode Off On default configuration
Tsdd
S-Wire CNTL T_Wake up
Toff Change configuration Amplifier Off
Figure 3. S-Wire / Enable Timing Diagram
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TYPICAL OPERATING CHARACTERISTICS
100 90 80 EFFICIENCY (%) EFFICIENCY (%) 70 60 50 40 30 20 10 0 Vdd = 3.6 V RL = 8 W 100 90 80 70 60 50 40 30 20 10 0 Vdd = 3.6 V RL = 4 W
0
200
400
600
800
1000
0
250
500
750 Pout (mW)
1000
1250
1500
Pout (mW)
Figure 4. Efficiency vs. Pout
100 100
Figure 5. Efficiency vs. Pout
10 THD (%)
Vdd = 2.5 V THD (%) Vdd = 2.7 V Vdd = 3.6 V Vdd = 4.2 V Vdd = 5.0 V Vdd = 5.5 V
10
1
Vdd = 3.0 V
1
Vdd = 2.5 V Vdd = 2.7 V Vdd = 3.0 V Vdd = 3.6 V Vdd = 4.2 V Vdd = 5.0 V Vdd = 5.5 V
0.1
0.1
0.01
10
100 Pout (mW)
1k
10 k
0.01
10
100 Pout (mW)
1k
10 k
Figure 6. THD+N vs. Pout, RL = 8 W
10 1
Figure 7. THD+N vs. Pout, RL = 4 W
Pout = 250 mW THD+N (%) THD+N (%) 1 0.1
Pout = 500 mW
0.1
0.01
Pout = 250 mW
0.01
10
100
1k FREQUENCY (Hz)
10 k
100 k
0.001
10
100
1k FREQUENCY (Hz)
10 k
100 k
Figure 8. THD+N vs. Frequency, Vdd = 2.5 V
Figure 9. THD+N vs. Frequency, Vdd = 3.6 V
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NCP2824
TYPICAL OPERATING CHARACTERISTICS
1 0 -10 0.1 Pout = 999 mW PSRR (dB) Pout = 250 mW Pout = 500 mW 0.01 -20 -30 -40 -50 -60 -70 0.001 10 100 1k FREQUENCY (Hz) 10 k 100 k -80 10 100 1k FREQUENCY (Hz) 10 k 100 k Vdd = 3.0 V Vdd = 3.6 V Vdd = 5.0 V
THD+N (%)
Figure 10. THD+N vs. Frequency, Vdd = 5 V
0 -10 PEAK VOLTAGE (V) -20 PSRR (dB) -30 -40 -50 -60 -70 -80 10 100 1k FREQUENCY (Hz) 10 k 100 k Vdd = 3.0 V Vdd = 3.6 V Vdd = 5.0 V 4.0 3.5 3.0 2.5 2.0 1.5
Figure 11. PSRR vs. Frequency (Inputs Grounded, Gain = 12 dB, Cin = 1 mF)
VDD = 5 V Temp = 25C 3.15 V 2.70 V 2.25 V 1.80 V Vpeak Target = 3.6 V
1.35 V 1.0 0.9 V 0.5 0 0 0.45 V 0.2 0.4 0.6 Vin (V) 0.8 1.0 1.2
Figure 12. PSRR vs. Frequency (Inputs Grounded, Gain = 18 dB, Cin = 1 mF)
25 20 THD+N (%) 15 10 5 0 10% 8% 6% 4% 2% 1% 0 0.2 0.4 0.6 Vin (V) 0.8 1.0 1.2 25 20 THD+N (%) 15 10 5 0
Figure 13. Peak Output Voltage in Power Limit vs. Input Voltage (rms) and Power Limit Settings, Av = 12 dB
PVDD = 3.6 V Temp = 25C THD+N Target = 20%
THD+N Target = 20%
PVDD = 3.6 V Temp = 25C
15%
15% 10% 8% 6% 4% 2% 1% 0.6 Vin (V)
0
0.2
0.4
0.8
1.0
1.2
Figure 14. THD+N vs. Input Voltage (rms) and Non Clip Settings, RL = 8 W, Av = 12 dB
Figure 15. THD+N vs. Input Voltage (rms) and Non Clip Settings, RL = 4 W, Av = 12 dB
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NCP2824
Detailed Operating Description
General Description AGC Operation
The NCP2824 is a Mono class D audio amplifier featuring a preamplifier stage, a PWM stage and an H-Bridge stage with an automatic Gain control circuitry which performs the non clipping function.
Non Clipping Function
The AGC operation defines the timings when the non clipping function is engaged. The typical values are described in the Electrical Table ("AGC Section"). Attack time (Ta): is defined as the minimum time between two gain decrease. Hold time (Th): is defined as the minimum time between a gain increase after a gain decrease. Release time (Tr): is defined as the minimum time between two gain increase. The following pictures depict the NCP2824 non clipping operation.
Th Ta Tr
In the presence of an exceeded input signal, when the audio signal is going to be clipped, the gain of the audio amplifier automatically decreases as defined by the AGC operation. The maximum level of THD is programmable and can be set by a final user through the single wire interface (see table n1). At the same time, the battery voltage is continuously monitored. The output signal is adapted to the dynamic battery voltage (Vdd) in order to avoid distortion due to supply voltage fluctuation like GSM burst. This function solution allows the chip to maximize the sound pressure level while maintaining a controlled THD level. The following picture depicts the non clipping operation.
Without Non clip function
VP
VP/2
With Non clip function
Single Wire Interface Operation Figure 16. Output of the Amplifier during a Line Transient on the Battery Voltage Power Limit Function: Speaker Protection
In addition to the non clipping function, a Power limit function is embedded in the NCP2824 in order to protect speakers from excessive output signal levels. When the output signal exceed this limit, the ??? Thus, the final user can use the Single Wire interface to program the maximum voltage rated by the speaker or to disable this power limit protection.
The single wire interface allows changing the default configuration of the NCP2824. After Wake up, the NCP2824 is configured with: * AGC enable * Non Clip + Power limit * Gain = 18 dB * THD max = 1% The following table described all the NCP2824 configurations.
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Table 4. NCP2824 CONFIGURATION
Pulse Counting 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 NOTE: NC+L NC Power Limit Control Reset Gain Control THD Control Register AGC Description AGC disable AGC Enable Reset configuration Gain = 12 dB Gain = 18 dB 1% 2% 4% 6% 8% 10% 15% 20% Non Clip + Power limit Non Clip only 0.45 VPeak 0.9 VPeak 1.35 VPeak 1.8 VPeak 2.25 VPeak 2.7 VPeak 3.15 VPeak 3.6 VPeak The given values are typical for Vdd = 3.6 V and TA = 25C characterized
use input capacitors when the differential source is not biased or in single ended configuration. In this case it is necessary to take into account the corner frequency which can influence the low frequency response of the NCP2824. The following equation will help choose the adequate input capacitor.
fc + 1 2 @ p @ 75 @ 10 3 @ Cin
Over Current Protection
This protection allows an over current in the H-Bridge to be detected. When the current is higher than 2 A, the H-Bridge is positioned in high impedance. When the short circuit is removed or the current is lower, the NCP2824 goes back to normal operation. This protection avoids over current due to a bad assembly (Output shorted together, to Vdd or to ground).
Layout Recommendations
For Efficiency and EMI considerations, it is strongly recommended to use Power and ground plane in order to reduce parasitic resistance and inductance. For the same reason, it is recommended to keep the output traces short and well shielded in order to avoid them to act as antenna. The level of EMI is strongly dependent upon the application. However, ferrite beads placed close to the NCP2824 will reduce EMI radiation when it is needed. Ferrite value is strongly dependent upon the application.
Built-in Low Pass Filter
This filter allows the user to connect a DAC or a CODEC directly to the NCP2824 input without increasing the output noise by mixing frequency with the DAC/CODEC output frequency. Consequently, optimized operation with DACs or CODECs is guaranteed without additional external components.
Decoupling Capacitors Figure 17. Example of PCB Layout
The NCP2824 requires a correct decoupling of the power supply in order to guarantee the best operation in terms of audio performances. To achieve optimum performance, it is necessary to place a 4.7 mF low ESR ceramic capacitor as close as possible to the VDD pin in order to reduce high frequency transient spikes due to parasitic inductance (see Layout considerations).
Input Capacitors Cin
Components Selection To achieve optimum performance, one 4.7 mF 6.3 V X5R should be used to bypass the power input supply (VDD). Also particular care must be observed for DC-bias effects in the ceramic capacitor selection. Smaller case-size and higher DC bias voltage is preferred. Some recommended capacitors include but are not limited to: 4.7 mF 6.3 V 0603 TDK: C1608X5R0J475MT 0.95 mm max.
Thanks to its fully differential architecture, the NCP2824 does not require input capacitors. However, it is possible to
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Example of Application Schematic
BATTERY C1 4.7 mF/6.3 V
Differential Audio Input Output from microcontroller
INP
VDD OUTP
INN OUTN CNTL PGND AGND U1 NCP2824
Figure 18. Differential Configuration
BATTERY C1 4.7 mF/6.3 V
Single Ended Audio Input
INP INN Output from microcontroller
VDD OUTP
OUTN CNTL PGND AGND U1 NCP2824
Figure 19. Single Ended Configuration
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PACKAGE DIMENSIONS
9 PIN FLIP-CHIP CASE 499AL-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. MILLIMETERS MIN MAX 0.540 0.660 0.210 0.270 0.330 0.390 1.450 BSC 1.450 BSC 0.290 0.340 0.500 BSC 1.000 BSC 1.000 BSC
4X
-A- D -B- E
0.10 C
TOP VIEW 0.10 C 0.05 C -C-
SEATING PLANE
A
DIM A A1 A2 D E b e D1 E1
A2 A1 SIDE VIEW D1 e
C B A
e
1 2 3
E1
9X
b
0.05 C A B 0.03 C BOTTOM VIEW
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